1. Field of the Invention
The present invention relates to electronics, and, in particular, to circuits, such a phase-lock loops, having oscillators.
2. Description of the Related Art
A phase-lock loop (PLL) is a circuit that generates a periodic output signal that has a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-lock loop is the charge-pump PLL, which is described in Floyd M. Gardner, "Charge-Pump Phase-Lock Loops" IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, November 1980, the teachings of which are incorporated herein by reference.
FIG. 1 shows a block diagram of a conventional charge-pump phase-lock loop 100. Phase/frequency detector (PFD) 102 compares the phase .theta..sub.IN of the input signal F.sub.IN to the phase .theta..sub.FB of the feedback signal F.sub.FB and generates an error signal: either an up signal U (when .theta..sub.IN leads .theta..sub.FB) or a down signal D (when .theta..sub.FB leads .theta..sub.IN), where the width of the error signal pulse indicates the magnitude of the difference between .theta..sub.IN and .theta..sub.FB.
Charge pump 104 generates an amount of charge equivalent to the error signal (either U or D) from PFD 102. Depending on whether the error signal was an up signal or a down signal, the charge is either added to or subtracted from the capacitors in loop filter 106. For purposes of this explanation, loop filter 106 has a relatively simple design, consisting of a capacitor C.sub.S in parallel with the series combination of a resistor R and a relatively large capacitor C.sub.L. As such, loop filter 106 operates as an integrator that accumulates the net charge from charge pump 104. Other, more-sophisticated loop filters are of course also possible. The resulting loop-filter voltage V.sub.LF is applied to voltage-controlled oscillator (VCO) 108. A voltage-controlled oscillator is a device that generates a periodic output signal (F.sub.OSC in FIG. 1), whose frequency is a function of the VCO input voltage (V.sub.LF in FIG. 1). In addition to being the output signal from PLL 100, the VCO output signal F.sub.OSC is used to generate the feedback signal F.sub.FB for the closed-loop PLL circuit.
Optional input and feedback dividers (110 and 112) are placed in the input and feedback paths, respectively, if the frequency of the output signal F.sub.OSC is to be either a fraction or a multiple of the frequency of the input signal F.sub.IN. If not, the input and feedback dividers can both be considered to apply factors of 1 to the input and feedback signals, respectively.
Due to the effect of the feedback path in PLL 100, the steady-state output signal F.sub.OSC will have a fixed phase relationship with respect to the input signal F.sub.IN. Unless some phase offset is purposely added, the phases of the input and output signals will be synchronized with minimal offset.
Voltage-controlled oscillators, such as VCO 108 of FIG. 1, are devices that are often designed for a wide range of applications (e.g., signal frequencies from 40 KHz to 400 MHz) Such VCOs are often designed with a number of operating curves (i.e., voltage in vs. frequency out), where the frequency range of any one curve is only a fraction of the total operating range of the VCO. FIG. 2 shows a hypothetical set of eight operating curves for a VCO. A special digital control input N is used to select one of the operating curves. The process of selecting a VCO operating curve is called trimming.
For low-noise PLL applications, it is important for VCO 108 in FIG. 1 to have a relatively low gain. This implies that the slope of the selected VCO operating curve should be relatively low, such as those shown in FIG. 2. A particular PLL application may have a specific desired frequency or desired frequency range for the VCO. For example, in one application, the PLL may be needed to generate a nominal 100-MHz output signal. To achieve the desired PLL operations, the VCO is trimmed by selected the operating curve (e.g., N=3 in FIG. 2) whose center frequency F.sub.CTR is close to the desired nominal PLL output frequency.
Under ideal circumstances, corresponding operating curves (i.e., those having the same digital control input value) in all VCOs of the same design would have the same center frequencies and slopes. In this case, for a particular PLL application, the same VCO operating curve could be selected for each and every PLL instance. However, in the real world, due to variations during device fabrication, the characteristics of the operating curves will vary from VCO to VCO. For example, the operating curves shown in FIG. 2 could shift up or to the right, and even have differing slopes. Nor are they all necessarily linear. As a result, for some applications, the VCOs in different PLL instances may need to be trimmed with different digital control input values N to select the appropriate VCO operating curve for the desired output frequency.
Conventionally, each VCO is tested in the factory to characterize its set of operating curves to pre-determine which digital control input values are appropriate for different desired output frequencies. When a particular VCO is selected for a particular application, such as PLL 100 of FIG. 1, the appropriate trim setting (i.e., the particular digital control input value N that corresponds to the desired output frequency) is permanently burned into the device (e.g., by blowing fuse links). This factory testing and hard-wiring of the VCO adds to the costs of manufacturing the PLLs. It also limits the operating frequency range of each PLL to the permanently selected operating curve.